Modern processors often include new features, for example, to improve security or support virtualization or multithreading, and/or new instructions to provide operations that are computationally intensive, but offer a high level of data parallelism that can be exploited through an efficient implementation using various data storage devices, such as for example, single instruction multiple data (SIMD) vector registers.
For many of these processors compiler adaptation lags far behind the hardware release, so the new features, instructions and/or resources are under utilized.
On the other hand, fault tolerance and fault detection features are not typically applied to these new features, instructions and/or resources in high-production processors because the implementation costs exceed the benefit. However, reducing the dimensions and increasing the number of transistors in a package and/or processing elements in a multiprocessor, while making devices faster and more efficient, increases the probability of faults due to alpha particles and other causal factors.
Additionally, there are some extreme environments in which fault tolerance is a highly desirable feature of computer systems. For example, a configurable fault tolerant processor (CFTP) was developed by the Space Systems Academic Group at the Naval Postgraduate School using field programmable gate arrays (FPGAs). It was then deployed as an experimental payload on board the United States Naval Academy's (USNA) MidSTAR-1 satellite. A second CFTP system, CFTP-2, was deployed as an entirely ground-based system and was tested in a proton beam using the University of California at Davis' cyclotron.
Binary translation is the emulation of one instruction set by another through translation of code. Sequences of instructions are translated from the source to the target instruction set. Static binary translation aims to convert all of the code of an executable file into code that runs on the target architecture without having to run the code first, as is done in dynamic binary translation. This is very difficult to do correctly, since not all the code can be discovered by the translator. For example, some parts of the executable may be reachable only through indirect branches, whose value is known only at run-time.
Dynamic binary translation looks at a short sequence of code—typically on the order of a single basic block—then translates it and caches the resulting sequence. Code is only translated as it is discovered and when possible branch instructions are made to point to already translated and saved code. In some cases such as instruction set simulation, the target instruction set may be the same as the source instruction set, providing testing and debugging features such as instruction trace, conditional breakpoints and hot spot detection. While such implementations may provide debugging and software/hardware development support, they are not typically directed to fault tolerance or fault detection. Additionally, binary translation techniques typically do little to improve utilization of new features, instructions and/or resources.
Some compiler techniques have sought to directly target features of hardware. These techniques have been applied, for example, to FPGA technology. A compiler may take high level source code as an input and compile the source code to produce FPGA logic as an output. In general, such FPGA implementations may limit performance advantages otherwise available for example, from very-large-scale integration (VLSI) and their implementations may additionally be larger and/or heavier, and may require higher supply voltages.
To date, potential solutions to such under utilization, fault tolerance, performance and efficiency limiting issues have not been adequately explored.